1. Field of the Invention
This invention relates to computer systems, and particularly to those that provide a hardware mechanism for interrupting program execution.
2. Description of Related Art
Most microprocessors, and indeed more general computing systems, provide at least two different levels of interrupt priority, which may be referred to as High Priority and Low Priority. For simplicity, the description herein begins with a focus on systems having only two such levels of interrupt priority. Low Priority interrupts preempt the normal flow of microprocessor code execution, while High Priority interrupts preempt both the normal flow of code execution, as well as Low Priority interrupts.
Typically, events with a relatively low bandwidth, such as keyboard and mouse operations, are assigned to the Low Priority interrupt, while higher bandwidth events, which could include, for example, responses to USB buffering, MP3 buffering, or Graphics Cards, are assigned to the High Priority interrupt.
Interrupt sources are often pre-assigned to either Low or High interrupt connections as part of the integrated circuit (IC) fabrication process. Event priorities are therefore effectively “hard-wired” into many IC designs before software for the IC is fully developed. Pre-assignment of interrupt priorities can create system design problems, especially for interrupts that are not easily classified as high bandwidth or low bandwidth, or for interrupts that vary in classification.
For example, a UART requires a much higher bandwidth than does a keyboard (Low Priority Interrupt), but a significantly lower bandwidth than a Graphics Controller device (High Priority Interrupt). If a UART is assigned the same interrupt priority as the Graphics Controller device, there is a danger than the Interrupt Service Routine (ISR) associated with the Graphics Controller will not receive timely attention while a UART ISR is in progress. Conversely, if a UART interrupt is assigned the same interrupt priority as lower bandwidth devices, such as a keyboard, then the keyboard interrupt may prevent the UART ISR from receiving timely attention.
Because the prior art forces designers to prioritize interrupts at the time of IC manufacture, which creates potentially serious problems for software development, there is a need for an improved method and apparatus for controlling the assignment of interrupt priorities.